3D chip arrangement including memory manager
Originating portfolio: TECH
Estimated expiration: 2026-Oct-05
Listed For Sale
Initial bid date: 2018-May-01
Potentially relevant companies (12): Analog Devices, Inc., Broadcom Corporation, GLOBALFOUNDRIES Inc., Integrated Device Technology, Inc., Intel Corporation, NXP B.V., Silicon Laboratories Incorporated, STMicroelectronics Incorporated, Taiwan Semiconductor Manufacturing Company, Ltd., Toshiba Corporation, United Microelectronics Corporation, Xilinx Incorporated
Products & technologies (2): Semiconductor:Memory, Semiconductor:Packaging
Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
1. A chip arrangement comprising:
a plurality of dies, wherein at least some of said dies are stacked face-to-face on top of each other and connected via sockets arranged on the respective faces in predefined patterns, wherein the sockets collectively form a bus that runs through all of the stacked dies;
said dies comprising
at least one memory die comprising at least one memory module, and
at least one logic die comprising at least one subsystem;
said chip arrangement further including a memory management unit connected to said at least one memory die and said at least one logic die, wherein said memory management unit is adapted for managing memory accesses from said at least one subsystem to said at least one memory module via the bus.
Availability date: Available now
Interested in licensing a slice of this patent? Contact us to take the next step, or read about our method to understand the logistics.